My bad..... Made a blunder with the capacitor multiplier schematic in the last post...
This is the correct schematic.
I forgot about the potential divider for biasing the MOSFET. My bad.
In doing so, we will reduce the B+ by 5% & also provide a short term regulation of +/-10%. Hence, smooth out sudden mains voltage fluctuation within to 5%.
In the long term sense, the B+ will track the mains voltage fluctuation.
Under New Management
Since we happened to have a gyrator in the circuit. Might as well let them do what they do best i.e. reduce Zo to single digit & excellent ripple reduction.
Now I can reshuffle the component values of the CLC to achieve the damping factor which I am looking for, highest B+ possible & lessen capacitance further.
Added a 220R 5W resistor in series to the choke, this was not an option earlier as it will add on the PSU Zo, with this, I can reduce 120uf to 47uf.
I could had use 10uf at the last cap, but the gyrator only mimic a huge capacitor without actually storing any real energy, so using a 47uf as reservoir seems reasonable.
Also, 3 more snubber capacitors for the rectifier, now, there is a snubber cap for every diode in the bridge rectifier. This will work better yet still not too much work...
We loss about 15V on the B+ with the gyrator & CLC amendments, but I consider that a bargain with the added slow-ramp, cleaner, stable B+, better damping pattern & reduced Zo significantly.
..........PREVIEW Part 8..........
Closure
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